Electronic Design: Advanced SoC Development Uses Next-Gen IP Integration Tools

Network-on-chip (NoC) interconnect IP and SoC integration technology enables higher product performance with lower power consumption and faster time-to-market.

The considerable growth of the number of logical cores in a chip increases the number of networks-on-chip (NoCs) per system-on-chip (SoC), fueling design complexity. Demand is on the rise for better power, performance, and area (PPA) utilization, creating a pressure for advanced levels of physical awareness and optimization in NoC and SoCs. In addition, rapid innovation cycles and the rush to market need silicon-proven IP, as anything else is too risky.

Arteris is addressing these demands for SoC innovation, providing semiconductor system IP for the acceleration of SoC development. The company’s Network-on-Chip Interconnect intellectual property (IP) and SoC integration technology enable higher product performance with lower power consumption and faster time-to-market.

Using these proprietary NoC techniques for on-chip communications results can help meet project specifications, reduce project risk, speed time-to-market, and improve SoC economics when compared to legacy and manually derived interconnects.

Arteris interconnect IP and SoC automation technologies, used alongside various processor architectures, are eventually mapped into semiconductor manufacturing technologies. The company’s NoC interconnect IP technology is highly differentiated, with the ability to optimize IP topology with physical awareness, making it a part of the ecosystem with firms like Cadence, Synopsys, and Siemens EDA. It’s also implemented in semiconductor manufacturing ecosystems, such as those of GlobalFoundries, Intel Foundry Services, Samsung Foundry, and TSMC.

To watch the conversation on the benefits of NoCs for SoCs on Electronic Design, click here.