解决关键的 SoC 设计挑战
CodaCache 末级缓存 IP
提高 SoC设计的性能和效率
可配置的系统
CodaCache 的可配置性可以微调设置以获得最佳性能，在特定场景中释放缓存的全部潜力。
更快的性能
可快速便捷的访问需经常访问的数据，无需访问主内存，从而提高了性能。
无缝集成
AXI 支持可实现组件之间的高效通信，轻松集成到现有的 SoC 设计中并加快开发过程。
CodaCache 主要功能
- 灵活的物理布局
- 可配置的代理缓存
- 可配置的探听过滤器
- 关联性
- 每路可配置暂存器存储器
- 路径分区
- 性能检测
- 性能模型
- 功能安全
- 图形用户界面（GUI）
- 通过硬件缓存刷新来辅助一致性管理
CodaCache产品优势
频率高，延迟时间短
通过优化缓存和高效的数据访问，提高了系统和IP的性能
低功耗
减少片外主存访问次数，从而降低功耗
较小的芯片面积
通过其高度分布的体系结构和可配置的高速缓存分区
配置简单
直观和用户友好的界面
自动验证
通过自动验证生成，可以节省数百个小时的工时
缩短项目周期
缩短项目周期
访问我们的 NoC Technology页面了解更多
CodaCache产品选项
Cache Line Options
- Up to 128 Bytes
- Up to 256 Bytes
- Up to 512 Bytes
The Arteris CodaCache reduces memory bottlenecks and saves power by allowing system-on-chip to employ a highly configurable last-level cache rather than solely communicating with off-chip memory. Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.
The Linley Group
Mike Demler, Senior Analyst, The Linley Group
Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
Freescale
Fares Bagh, Vice President of R&D, Freescale
- CodaCache datasheet
- Articles
- Reducing SoC Power With NoCs And Caches | Semiconductor Engineering
- Turbocharging Cost-Conscious SoCs With Cache | Semiconductor Engineering
- Technical Papers
- Webinars