Learn about the inspiring career journey of Charles Janac. Discover his advice for early-career engineers and his passion for technology.

Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor

At a time when artificial intelligence (AI)-centric system-on-chips (SoCs) are growing in size and complexity, network-on-chip (NoC) tiling hand in hand with mesh topology can support faster development of compute chip designs.

Deploying commercial NoC IP and adopting advanced SoC integration tools empowers designers to better manage the growing number of IP blocks, ensure data consistency and meet the PPA requirements of today’s applications.

Multi-die architectures demand expert planning to ensure connectivity and performance. To address these challenges, structured assembly methodologies complemented by IP-XACT standards have become essential to provide a clear chip design framework. Explore new solutions to improve performance and quality.

The evolution from monolithic dies to multi-die systems using chiplets marks a pivotal advancement in semiconductor technology. It takes an ecosystem of partners to develop and refine multi-die systems effectively and Arteris is here to help.

Enhancing SoC CPU performance doesn’t have to break the bank with high-performing IP cores. Learn how cost-effective optimization of cache memory systems can maximize CPU output.

Optimized interconnect topology and system partitioning, give engineering teams an efficient strategy to achieve performance and cost targets.