Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
Learn how ISO 26262 Part 11 helps semiconductor architects build safer automotive SoCs through architectural planning, automation, and functional safety.
EDN: Hardware security verification must go beyond functional testing
This article explains why functional testing alone cannot uncover the unintended data paths and hardware–firmware interactions that create security risks, and how Cycuity Radix enables teams to define verifiable security requirements, detect violations and measure security coverage across simulation and emulation workflows.
TechRadar: Data movement is the new performance battleground in semiconductor design
The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.
Electronic Design: The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement
The article explores why predictable, scalable data movement is becoming a critical architectural requirement for AI systems as compute complexity and bandwidth demands continue to grow.
Embedded: Last-Level Caches Matter Even More in the HBM Era
The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.
What the Cyber Resilience Act means for the future of chip design
The EU Cyber Resilience Act is reshaping semiconductor security, making cybersecurity, compliance, and lifecycle management core design priorities.
Semiconductor Engineering: Reducing Avoidable Memory Trips In HBM Systems
As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.
Semiconductor Engineering: Using SystemC TLM Modeling To Solve AI Data Movement Challenges
SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates architectural decision-making in the article.
EDN: How data movement defines performance for AI silicon
This article explores how AI chip performance is increasingly constrained by data movement rather than raw compute power, highlighting the growing role of network-on-chip (NoC) architectures, chiplets, cache hierarchies, and physically aware design in modern AI SoCs. Learn more about how scalable interconnects, automation, and system-level design approaches help overcome AI-era bottlenecks in the article.
Design & Reuse: A Repeatable Framework for Hardware Security Assurance
This article explores how hardware security assurance is evolving into a structured, repeatable process for evaluating third-party IP in increasingly complex SoC and RISC-V designs.