Magillem Registers

Get to market faster with an error-free system memory map

Magillem Registers

Overview

Accelerate large-scale SoCs schedules with effective hardware/software interface development

Magillem® Registers offers a single source of truth methodology, which not only targets the traditional need to manage registers, but also addresses today’s hardware and software integration challenges for large-scale SoCs.

Quick and scalable automated implementation with Magillem Registers helps cut time to market in half for hardware/software interface (HSI) generation.

Straightforward register intent capture

Magillem Registers translates register specifications into executable design code by automatically importing the register descriptions from different sources and formats.

Automatically checks the accuracy of the information (overlaps, configurability, reserved empty spaces, …).
Enables close collaboration between hardware, software, and tech doc teams through a single source of truth methodology for consistently generated data.
Comprehensive HSI automation helps ensure improved quality design and increased productivity.

Straightforward Register Intent Capture

Automatically Generate Consistent Data

Automatically generate consistent data

Magillem Registers is a true cross-compiler with over 1,000 functional, behavioral, syntactic, and semantic error checks. It supports various formats and generates multiple outputs simultaneously.

Generated data is consistent and complete, which gives verification teams an up-to-date generated register model to work from.

Error-free system map generation

Full Magillem Registers and Magillem Connectivity integration synchronizes connectivity and memory map information:

Calculate and display the system map from the selected initiator.
Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
Check that all the software visible elements (registers or memory regions) in connected targets are present in the memory map.

Error-Free System Map Generation

Magillem Registers key features

Single database: Import and capture memory map information into a single database for generating RTL, digital verification, firmware, and documentation.
Various input formats: Provides for CSRSpec language, SystemRDL, IP-XACT 2009/2014/2022, spreadsheets, and more.
Extensive error/syntax checking: More than 1,000 error checks.
Alternative UVM backdoor methodology: Supports high performance on large designs.
Advanced features: Registers broadcast/alias, virtual registers, wide memories and atomic access support.
Tool Integration: Tight link with the connectivity tool to generate a system address map when both tools are combined.

Show More Features

Explore additional Magillem Registers features, download the datasheet.

Full NoC integration for automated flow

Leverage SoC connectivity information:

Increase productivity with reduced process.
Improve quality with early error detection by checkers.

NoC Integration Automated Flow

Magillem Registers product benefits

Easy specification adjustment

Rapid iteration with updated information across design teams helps ensure data consistency.

Agile design process

Clearly defined process to ensure best practices and early engagement of the entire design team.

Scalable and expansive

Compiles over 5 million registers and can be used on large-scale SoC memory maps.

Automated and efficient

Helps reduce tedious and error-prone tasks with a fully automated flow, and shortens the overall process.

Accurate and consistent

Hardware, software and documentation are all in sync to ensure accuracy and cross-team consistency through a single source of truth.

Quality assurance

Catch errors at the data entry stage with the memory map information before running any simulation.

Productivity booster

Accelerate the schedule with a correct-by-construction software interface.

Magillem Registers Product Options

Seamlessly Integrated Extensions to the Base Feature Set

Architectural: System Map Import and Generation

Automatically create the entire IP-XACT platform from the xls file input describing the system map
Automatically create the entire IP-XACT platform from the xls file input describing the system map
Enable keeping both software and hardware ends synchronized

Safety: Functional Safety Reg Bank

Single/Double Error Detection: register byte parity bit and register duplication
SW and HW Interface Protection: AMBA check types
Error reporting: error output bits and protocol error signaling
Ensure support of safety requirements for automotive industry

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Featured Solution

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.

Magillem Platform

Powerful comprehensive SoC integration automation

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog/SystemVerilog support
HDL Import	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
Assembly	Rule-based connectivity
	Bus/signal split/tie/open/feedthrough
	Glue logic insertion
RTL Netlist Generation	Configurable header
	Keep parameter expressions
	Signals/netname/tie management
Hierarchical Manipulations	Merge, Flatten, Move operations
Hierarchical Manipulations	Parameter propagation
IP Update	Rename/resize/delete/merge
IP Update	User mapping rules definition
Diff and Merge	Accept/Reject any change
Diff and Merge	Conflict resolution wizard
Import Memory Map Description	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description

Resources

White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.

Datasheets

Magillem® Registers

Podcasts

Presentations

Solution Briefs

Accelerate, Optimize, and Secure AI-Based SoC Designs with Arteris

Videos

Webinars

Three Perspectives on System Design Challenges

White Papers

Quick Reference Guides

7 Ways Magillem Registers Streamlines Hardware-Software Interface Design

Frequently Asked Questions

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