Arteris Celebrates One Year in Poland with New and Expanded Partnerships
Arteris marked the first anniversary of its Krakow engineering hub, highlighting a year of growth, innovation, and deeper integration into Europe’s semiconductor ecosystem. The milestone included expanded partnerships with leading Polish universities, reinforcing collaboration in research, education, and talent development. Through ongoing contributions to NoC IP and SoC integration technologies, the Krakow team plays a key role in advancing complex chip design and a broader focus on strengthening Europe’s semiconductor capabilities.
Semiconductor Engineering: System Integration With Standards-Based Automation
As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.
EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
EE Times: Smarter SoC Design for Agile Teams and Tight Deadlines
Advanced NoC automation helps lean SoC teams meet tight deadlines by reducing complexity, cutting design time, and improving power and performance efficiency.
Design & Reuse: Enabling Chiplet Design Through Automation and Integration Solutions
Explore how chiplet-based designs overcome SoC limitations. Arteris’ multi-die solution enables connectivity across chiplets, supporting coherent and non-coherent traffic and intelligent dataflow management.
EDN: Chiplet basics: Separating hype from reality
Planning chiplet-based designs is underway. Yet, uncertainty continues to swirl around chiplet architecture and ready-to-use technologies. New innovations are on the horizon.
Design & Reuse: Automating NoC Design to Tackle Rising SoC Complexity
Modern SoCs typically include between 5 and 20 individual NoC instances, consuming around 10–13% of the total silicon area. However, existing methodologies, especially in light of growing register demands, are proving inadequate. This leads to extended development cycles, frequent design iterations, and heightened schedule risks. To address these challenges, automated NoC generation provides a scalable and efficient solution for managing increasing design complexity. Learn more about how automation is transforming NoC design in this article.
Semiconductor Engineering: CSR Management: Life Beyond Spreadsheets
The hardware-software interface (HSI) that’s physically represented by control and status registers (CSRs) is a critical source of design risk. Mismanagement of CSRs contributes to a number of SoC failures. To avoid these setbacks, engineering teams need a robust, automated approach to CSR definition and management that ensures consistency across hardware and software.
EDN: Boosting RISC-V SoC performance for AI and ML applications
Modern SoC designs are more innovative and complex than ever, therefore RISC-V-based designs must address challenges like interoperability, hardware-software integration, and safety certifications to meet stringent performance and reliability standards. Learn more in this article.
Electronic Design: Breaking Barriers in SoC Design with Smart NoC Automation
As SoCs grow in complexity, manual NoC generation is no longer practical. Discover how automated NoC generation streamlines interconnect development to improve efficiency, scalability, and performance in advanced semiconductor designs.