EE Times: A Guide to Building Chiplets Today While Shaping Tomorrow’s Standards
Chiplet standards like UCIe, AIB, and BoW are still evolving, but design teams can start building with chiplets today by adopting packaging automation, structured IP metadata, and scalable interconnect fabrics that enable flexibility and future-proof integration. Learn how to design with chiplets now and help shape the standards of tomorrow in the article.
EDN: A Logically Correct SoC Design Isn’t an Optimized Design
Automation in SoC design is evolving beyond correctness toward true optimization. Just as modern GPS systems account for real-world traffic, AI-driven, physically aware automation for NoC design minimizes wire length, manages congestion, and adapts dynamically to design changes — closing the gap between a design that merely works and one that performs efficiently. Learn how smart NoC IP like FlexGen is redefining optimization in SoC design in the article.
Semiconductor Engineering: The Future Of SoC Design Is Data Movement
The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated, and physically aware interconnect solutions. This article explores the design requirements, pitfalls, and architectural strategies needed to meet the demands of next-generation SoCs while ensuring safety, security, and scalability. Learn more in the article.
Electronic Design: Speeding the Process of Building IPs, Chiplets, and SoCs
Designing modern SoCs and multi-die systems requires faster integration of thousands of IP blocks and chiplets while minimizing errors. Structured metadata standards like IP-XACT, combined with automation, are transforming this process by ensuring consistency, tool interoperability, and accurate hardware/software alignment across multiple abstraction levels. The article explores how evolving IP-XACT standards and tools like Arteris Magillem Packaging streamline integration, reduce complexity, and accelerate time to market. Explore to learn more.
Critical Safety Overview and Definitions
Overview of critical safety systems and functional safety standards in automotive, focusing on ISO 26262 compliance and its impact on SoC design and performance.
NoC Interconnect IP Improves SoC Power, Performance and Area
Explore how Arteris’ NoC interconnect IP enhances SoC power efficiency, performance, and area, driving advancements in complex semiconductor designs.
Design & Reuse: Efficient IP Packaging for Today’s SoC Integration
As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes reuse across projects. Learn more in the article.
Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.
RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem
As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and automation tools for seamless integration. From boosting bandwidth and cache coherency to simplifying system complexity, Arteris delivers the complete solution for next-generation RISC-V processors. Learn more in the article.