Semiconductor Engineering: Verification Experts Vs. Generalists
The increasing complexity of design is driving specialization and innovative approaches in verification — and some interesting arguments. Read the full discussion of the expert panel here.
EDN: How AI is changing the game for high-performance SoC designs
The rapid increase in SoC complexity has exceeded the capabilities of traditional NoC design methodologies. Learn more about the smart NoC IP alternatives in this article.
RISC-V: Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk
Discover how Arteris’ NoC soft tiling tech accelerates RISC-V processor cluster design, boosting scalability and reducing errors in complex SoCs.
Semiconductor Engineering: Top 5 Reasons Engineers Need A Smart NoC
As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. Learn how Arteris’ FlexGen smart NoC IP could help deliver future-ready SoCs.
SemiWiki: Is Arteris Poised to Enable Next Generation System Design?
The semiconductor industry is transitioning to multi-die designs driven by AI. Arteris is leading the way by tackling challenges like the ‘memory wall’ using cache-coherent NoC and Magillem technology for efficient IP management. Learn more in the article.
Electronic Design: AI Automation Builds Better NoCs
There are numerous challenges one has to overcome to build efficient network-on-chip (NoC) solutions. In this article, learn how AI is helping to improve NoC configuration and accelerate its development.
Semiconductor Engineering: Design Customization Puts Heavy Burden On Verification
Configurability causes an explosion in verification complexity, but the upside is verification engineers are gaining in stature.