Semiconductor Engineering: Reducing SoC Power With NoCs And Caches
The growing complexity of integrating multiple processing elements, memory systems and communication interfaces into a single SoC demands innovative solutions to optimize power efficiency. Arteris offers a comprehensive suite of IP products, including FlexNoC, Ncore and CodaCache that address these challenges.
Electronic Design: All About NoCs
Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor Bill Wong talks with Andy Nightingale, VP Product Management and Marketing at Arteris, about NoCs.
Design & Reuse: Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
A new trend is emerging in the design of high-end, multi-billion-transistor system-on-chip (SoC) devices and it is called “NoC tiling”. It’s an innovative approach that facilitates scaling, condenses design time, speeds testing, and reduces risk.
EDN: Why NoC tiling matters in AI-centric SoC designs
At a time when artificial intelligence (AI)-centric system-on-chips (SoCs) are growing in size and complexity, network-on-chip (NoC) tiling hand in hand with mesh topology can support faster development of compute chip designs.
Semiconductor Engineering: Managing Performance in Modern SoC Designs
Deploying commercial NoC IP and adopting advanced SoC integration tools empowers designers to better manage the growing number of IP blocks, ensure data consistency and meet the PPA requirements of today’s applications.
Semiconductor Engineering: Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly
Multi-die architectures demand expert planning to ensure connectivity and performance. To address these challenges, structured assembly methodologies complemented by IP-XACT standards have become essential to provide a clear chip design framework. Explore new solutions to improve performance and quality.
EDN: NoCs and the transition to multi-die systems using chiplets
The evolution from monolithic dies to multi-die systems using chiplets marks a pivotal advancement in semiconductor technology. It takes an ecosystem of partners to develop and refine multi-die systems effectively and Arteris is here to help.
EE Times: How to Turbo Charge Your SoC’s CPU(s)
Enhancing SoC CPU performance doesn’t have to break the bank with high-performing IP cores. Learn how cost-effective optimization of cache memory systems can maximize CPU output.
Semiconductor Engineering: Optimizing Interconnect Topologies For Automotive ADAS Applications
Optimized interconnect topology and system partitioning, give engineering teams an efficient strategy to achieve performance and cost targets.
Electronic Design: Adding Cache to IPs and SoCs
Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption.