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Tech Design Forum: Arteris extends safety and speed for NoC – Tech Design Forum
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EDN: Cache coherent interconnect IP pre-validated for Armv9 processors – EDN By Majeed Ahmad
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Electronics Weekly: Network-on-chip supports Arm v9 architecture and automotive functional safety
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All About Circuits: Arteris Revs New Version of Its Cache Coherent Interconnect IP
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Electronic Design: Certified Cache-Coherent Interconnect Supports Safety Applications
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FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling | Semiconductor Engineering
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Kalray, Arteris, Secure-IC, and Thales, Win the Call for Projects Related to the AI Acceleration Strategy of the “France Relance 2030 – Future Investments” Plan
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