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Podcast
SemiWiki: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale
Dan talks with Andy Nightingale from Arteris about new tiling capabilities and extended mesh topology support for network-on-chip IP products. They explore how these features address AI-driven chip design challenges.
Solution Brief
Accelerate AI-Driven Silicon Innovation with Arteris Multi-Die Solution
The Arteris Multi-Die Solution delivers flexible design scalability for chiplet-based systems, optimal PPA, highest quality-of-results (QoR), functional safety and broad standards support to achieve the fastest time to silicon.
Video
FlexGen Smart NoC IP from Arteris Revolutionizes Complex SoC Designs
FlexGen smart NoC IP enables automated NoC design with reduced manual effort, shorter iteration cycles, and expert-level quality of results. SoC design teams can realize faster time-to-market, optimized power plus performance, reduced wire length, and improved overall design economics with FlexGen.
Video
FlexNoC 5 Physically Aware Network-on-Chip IP
FlexNoC 5 physically aware network-on-chip IP incorporates physical constraint management across power, performance, and area (PPA). Get up to 5X faster physical convergence vs manual physical iterations and achieve PPA goals within schedule and budget constraints.
Video
Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
Magillem Registers is a comprehensive register design and management technology that accurately automates the hardware/software interface (HSI) to quickly develop chips and chiplets ranging from IoT devices to complex AI datacenter multi-die SoCs.
Video
Ncore™ Cache Coherent Network-on-Chip IP from Arteris
Ncore cache coherent NoC IP is scalable, configurable, and ISO 26262 certified. With Ncore, teams can derisk their SoC designs and deliver on their vision in record time, saving upwards of 50 years of engineering effort per project compared to manually generated solutions.
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