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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Podcast

SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski

SemiWiki’s Dan Nenni welcomes Michal Siwinski, CMO of Arteris, for an in-depth discussion of modern design architectures and the crucial role of Network-on-Chips (NoCs).
Podcast

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.
Podcast

SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac

Arteris CEO joins SemiWiki’s Daniel Nenni on Semiconductor Insiders Podcast to discuss the impact of using a physically aware NoC.
Boost-SoC-Efficiency-and-Speed-with-FlexGen-Smart-NoC-IP-Automation-White-Paper
White Paper

Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper

This white paper examines the challenges of manual NoC implementation and how smart automation improves NoC performance. Explore how FlexGen’s AI-driven heuristics minimize wire length, refine topology, and reduce latency, making it a transformative technology for AI, HPC, automotive, and other applications.
FlexGen™ Smart Interconnect IP Datasheet
Datasheet

FlexGen® Smart Interconnect IP

  • Automated non-coherent NoC IP generation with expert results
  • Significantly reduces NoC development time
  • 10x productivity boost over…
FlexGen® 1, FlexNoC® 5 & FlexWay® 5 Functional Safety Option
Datasheet

FlexGen® 1, FlexNoC® 5 & FlexWay® 5 Functional Safety Option

  • ISO 26262 ASIL D certifiable. Helps enable the highest level of functional safety.
  • Comprehensive safety features….
FlexNoC® Reliability Option for Enterprise Applications and Industrial Applications
Datasheet

FlexNoC® Reliability Option for Enterprise Applications and Industrial Applications

  • Enables robust reliability in enterprise SoC designs
  • Helps with seamless coordination of data and control signals…
FlexNoC® 5 and FlexGen® Reorder Buffer (ROB) Options
Datasheet

FlexNoC® 5 and FlexGen® Reorder Buffer (ROB) Options

  • Unlock high-speed data flow with concurrent memory channel reads and optimized interleaving.
  • Achieve seamless responsiveness by…
XL and 2XL Options for FlexGen® and FlexNoC® 5
Datasheet

XL and 2XL Options for FlexGen® and FlexNoC® 5

  • Advanced mesh editor
  • Efficient multicast and broadcast
  • VC-Link™ virtual channels; Source synchronous communications
  • HBMx support e.g. HBM2/HBM2E/HBM3 (via…
Accelerating Timing Closure for Networks on Chip NoCs With Physical Awareness
Infographic

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

The number of IP blocks in SoCs and across chiplets continues to grow. See how considering the floorplan information during the NoC architecture, combined with early estimation of pipeline stages can significantly reduce the time to physical closure.
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