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Presentation
Safety Considerations for Network-on-Chip (NoC) Development
This presentation illustrates functional safety challenges in system design and adherence to the ISO 26262 standard for automotive electronics. It highlights Network-on-Chip (NoC) safety mechanisms, including timeouts, IP Block isolation, and end-to-end interface protection.
Presentation
The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
Discover how networks-on-chips (NoCs) are revolutionizing AI/ML across sensors, edge devices, and data centers. This video presentation explores how NoCs enable rapid data movement, seamless component integration, and efficient chip-to-chip communication, paving the way for a new era of AI-powered devices.
Podcast
EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.
Podcast
EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs.
Podcast
Electronic Design: All About NoCs
Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor Bill Wong talks with Andy Nightingale, VP Product Management and Marketing at Arteris, about NoCs.
Podcast
EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V
The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.
Solution Brief
Accelerate, Derisk, and Secure RISC-V-based SoC Designs with Arteris
Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.
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