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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Cover for PDF - 8 Ways CodaCache IP Boosts SoC Design
Quick Reference Guides

8 Ways CodaCache IP Boosts SoC Design

Ensure efficient data movement with powerful, stand-alone, non-coherent cache IP designed to help you achieve performance and efficiency goals.
AI solution brief thumbnail
Solution Brief

Accelerate, Optimize, and Secure AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
CodaCache Helping to Break the Memory Wall
White Paper

CodaCache®: Helping to Break the Memory Wall

This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
Presentation

Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)

Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.
Presentation

FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)

Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics.
Presentation

Is the Missing Safety Ingredient in Automotive AI Traceability?

Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.
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