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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Cover for PDF - 7 Powerful Features of Magillem Connectivity that Streamline SoC Design
Quick Reference Guides

7 Powerful Features of Magillem Connectivity that Streamline SoC Design

Discover how to simplify SoC integration with automation that cuts development time, reduces manual errors, and helps ensure high-quality system assembly.
Presentation

Will it Blend? – Verifying the Hardware / Software Interface of Complex SoCs

This presentation highlights how Arteris SoC integration automation technologies streamline the blend of hardware, software, and verification components including VHDL, SystemVerilog, UPF, IP-XACT, and UVM to boost productivity and enable first-time silicon success.
AI solution brief thumbnail
Solution Brief

Accelerate, Optimize, and Secure AI-Based SoC Designs with Arteris

Optimize performance, power, and area for AI-driven SoCs from data centers to edge devices. Enable faster innovation in generative AI, physical AI, and autonomous systems with proven Arteris technology built for scalability, efficiency, and hardware assurance.
Chiplets: Opportunities and Challenges
Video

Chiplets: Opportunities and Challenges

Explore the challenges of chiplet interoperability and ecosystem collaboration and how leading companies are navigating this shift.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Making SoC Integration Simple – Achieve Higher Productivity and Quality
White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.
A Design Flow for Critical Embedded Systems
White Paper

A Design Flow for Critical Embedded Systems

In this paper by Airbus, Thales, STMicroelectronics, Arteris and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.
A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
White Paper

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.
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