AI workloads are transforming SoC design, driving the need for faster data movement, lower latency, and higher energy efficiency. As AI and accelerated computing scale across heterogeneous architectures, the Network-on-Chip (NoC) has become the backbone that determines system performance, power efficiency, and overall scalability. In this SemiWiki-hosted webinar, Andy Nightingale, VP of Product Management and Marketing at Arteris, and Piyush Singh, Principal Digital SoC Architect at Aion Silicon, explore key considerations for architecting NoCs optimized for AI-driven designs. The discussion covers AI communication patterns, physically aware NoC topologies, multi-die integration and memory coherence challenges, performance simulation techniques, and NoC partitioning strategies to support scalable, power-aware AI systems from data center to edge.