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TechRadar: Data movement is the new performance battleground in semiconductor design
The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.
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Embedded: Last-Level Caches Matter Even More in the HBM Era
The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.
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The AI Journal: Making chiplets work for AI requires more than connectivity
This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI
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