Multi-Die – Arteris

Semiconductor Engineering: How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore,

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TechRadar: Data movement is the new performance battleground in semiconductor design

The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.

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Semiconductor Engineering: Avoid The Hidden Bottleneck Of Integration At Scale

This Semiconductor Engineering article examines how SoC integration has become a major bottleneck as designs scale in complexity, with growing numbers of IP blocks, registers, and hardware/software interfaces.

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The AI Journal: Making chiplets work for AI requires more than connectivity

This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI

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EDN: How data movement defines performance for AI silicon

This article explores how AI chip performance is increasingly constrained by data movement rather than raw compute power, highlighting the growing role of network-on-chip (NoC) architectures, chiplets, cache hierarchies, and physically aware design in modern AI SoCs. Learn more about

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Chiplets 101: An Arteris Guide to Multi-Die Architecture

View our guide to chiplets and multi-die architecture, explaining interconnect, data movement, memory, and design strategies for scalable high-performance SoC systems.

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Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)

Modern system-on-chip (SoC) performance is no longer compute-bound. It is increasingly data-movement–bound and wire-limited.

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Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design

Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and

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EDN: Chiplet innovation isn’t waiting for perfect standards

As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling

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