Network-on-Chip (NoC)

Semiconductor Engineering: How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore,

Learn more about post

TechRadar: Data movement is the new performance battleground in semiconductor design

The article highlights why interconnect design must become a first-class architectural consideration, with quality of service, determinism and physically aware automation playing key roles across AI data centers, physical AI and multi-die systems.

Learn more about post

Electronic Design: The Missing Layer in AI Systems Design is Predictable, Scalable Data Movement

The article explores why predictable, scalable data movement is becoming a critical architectural requirement for AI systems as compute complexity and bandwidth demands continue to grow.

Learn more about post

Embedded: Last-Level Caches Matter Even More in the HBM Era

The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.

Learn more about post

Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project

As software-defined vehicles reshape the automotive industry, collaborative innovation is becoming essential to developing secure, scalable computing platforms. Learn how Arteris is contributing to the European RIGOLETTO project, helping advance next-generation automotive architectures through expertise in Network-on-Chip technology, RISC-V integration,

Learn more about post

The AI Journal: Making chiplets work for AI requires more than connectivity

This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI

Learn more about post

EDN: Model your IPs and your NoCs

As SoC and chiplet architectures become increasingly complex, effective modeling must extend beyond functional IP blocks to include the NoC interconnect fabric itself. This article highlights why NoCs have become critical determinants of system performance and explains the value of

Learn more about post

Semiconductor Engineering: Using SystemC TLM Modeling To Solve AI Data Movement Challenges

SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates

Learn more about post

EDN: How data movement defines performance for AI silicon

This article explores how AI chip performance is increasingly constrained by data movement rather than raw compute power, highlighting the growing role of network-on-chip (NoC) architectures, chiplets, cache hierarchies, and physically aware design in modern AI SoCs. Learn more about

Learn more about post

Chiplets 101: An Arteris Guide to Multi-Die Architecture

View our guide to chiplets and multi-die architecture, explaining interconnect, data movement, memory, and design strategies for scalable high-performance SoC systems.

Learn more about post

Tags: Network-on-Chip (NoC)

No results found