AI-Driven Development: Why Verification Matters More Than Ever
Discover why AI works best as an engineering partner, helping development teams explore solutions faster, while verification ensures reliable results.
Semiconductor Engineering: How Cache Coherency Simplifies AI Software
This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore, FlexNoC and FlexGen IP as complementary solutions for managing data movement.
Advancing Europe’s Automotive Innovation Ecosystem: Arteris Continues Its Work in the RIGOLETTO Project
As software-defined vehicles reshape the automotive industry, collaborative innovation is becoming essential to developing secure, scalable computing platforms. Learn how Arteris is contributing to the European RIGOLETTO project, helping advance next-generation automotive architectures through expertise in Network-on-Chip technology, RISC-V integration, and high-performance semiconductor design.
Semiconductor Engineering: Avoid The Hidden Bottleneck Of Integration At Scale
This Semiconductor Engineering article examines how SoC integration has become a major bottleneck as designs scale in complexity, with growing numbers of IP blocks, registers, and hardware/software interfaces.
The AI Journal: Making chiplets work for AI requires more than connectivity
This article explains why building successful AI chiplet architectures requires more than high-speed die-to-die connectivity. It explores how efficient data movement, protocol selection, coherency, and intelligent NoC architecture are critical to maximizing performance, scalability, and energy efficiency in next-generation AI systems.
Beyond Moore’s Law: Heterogeneous Computing and AI SoCs
As Moore’s Law slows, heterogeneous computing is driving AI, automotive, and data center innovation through specialized compute, chiplets, and advanced interconnects.
EDN: Model your IPs and your NoCs
As SoC and chiplet architectures become increasingly complex, effective modeling must extend beyond functional IP blocks to include the NoC interconnect fabric itself. This article highlights why NoCs have become critical determinants of system performance and explains the value of using consistent transaction-level, cycle-accurate, and RTL models throughout the design flow.
Cyber Defense Magazine: Securing The Unseen Why Data in Motion is the Next Cybersecurity Frontier
Securing the unseen: As AI drives massive data movement inside chips, organizations must secure and monitor data in motion to close hidden hardware attack surfaces.
Achieving ASIL Compliance in Automotive AI Systems
Learn how automotive companies are approaching ASIL compliance for AI systems using safety islands, redundancy, and functional safety architectures.
EE Times: AI-Accelerated Software Security Vulnerability Discovery: Is Hardware Next?
AI is accelerating software vulnerability discovery at unprecedented speed. Could semiconductor hardware be next, and how should the industry prepare?