AI-Accelerated Vulnerability Discovery: An Emergency in Software Security. Is Hardware Next?
Frontier AI models are accelerating vulnerability discovery at unprecedented scale, raising urgent questions about the future of hardware security.
What the steam engine can teach us about modern chip design
In 1712, a quiet breakthrough …
Chiplets 101: An Arteris Guide to Multi-Die Architecture
View our guide to chiplets and multi-die architecture, explaining interconnect, data movement, memory, and design strategies for scalable high-performance SoC systems.
Design & Reuse: Topology and Data Movement in Multi-Die Design
This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well as the need for configurable interconnects to ensure predictable system behavior. The piece also emphasizes the growing importance of unified integration tools to maintain consistency across complex, multi-die architectures.
The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
Modern system-on-chip (SoC) performance is no longer compute-bound. It is increasingly data-movement–bound and wire-limited.
Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs
Arteris and XuanTie have formed a deep partnership, leveraging the Ncore cache-coherent NoC IP as the core to build a “data highway” for high-performance RISC-V SoCs. Ncore paired with the XuanTie C930 delivers 30 GB/s/GHz bandwidth and 110-cycle latency, supporting expansion up to 16 cores. With its scalability, configurability, and safety advantages, Ncore has been validated within the XuanTie ecosystem, helping accelerate RISC-V toward high-performance applications.
Building Secure Chips: Why Hardware Security Assurance Is Now Essential
Hardware security is no longer optional. At DAC 2025, industry leaders share how teams are shifting from traditional verification to measurable security assurance without breaking budgets or schedules. Learn what’s changing, why it matters, and how to build trust into modern SoC design from the start.
EDN: Chiplet innovation isn’t waiting for perfect standards
As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling practical multi-die systems today. Learn more in the article.
EDN: Last-level cache has become a critical SoC design element
As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully configured around real workload behavior, with early decisions on sizing, banking, and partitioning validated through system-level simulation. The article also highlights Arteris’ CodaCache IP as a configurable LLC solution for scalable, intelligent data management across diverse applications. Learn more.
SemiWiki: Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
As RISC-V adoption grows across commercial and government programs, integrating third-party IP cores introduces supply chain security challenges that require structured, design-level assurance. This article highlights a scalable, CWE-based methodology demonstrated by Cycuity (an Arteris brand) with SiFive and BAE Systems that replaces checklist reviews with measurable, reusable security validation artifacts. By templating requirements, properties, and tests, teams can reduce NRE while strengthening confidence across RISC-V implementations. Learn more in the article.