Design & Reuse: A Repeatable Framework for Hardware Security Assurance
This article explores how hardware security assurance is evolving into a structured, repeatable process for evaluating third-party IP in increasingly complex SoC and RISC-V designs.
What the steam engine can teach us about modern chip design
In 1712, a quiet breakthrough …
Chiplets 101: An Arteris Guide to Multi-Die Architecture
View our guide to chiplets and multi-die architecture, explaining interconnect, data movement, memory, and design strategies for scalable high-performance SoC systems.
Semiconductor Engineering: Facilitating Complex SoC Design Through Automation And Integration
Automation and integration tools unify IP, connectivity, and software design, enabling scalable, efficient SoC development and reducing manual complexity. Learn more about how unified system definitions, automated interconnect generation, and coordinated design flows improve performance, productivity, and time-to-market in the article.
Arteris Celebrates One Year in Poland with New and Expanded Partnerships
Arteris marked the first anniversary of its Krakow engineering hub, highlighting a year of growth, innovation, and deeper integration into Europe’s semiconductor ecosystem. The milestone included expanded partnerships with leading Polish universities, reinforcing collaboration in research, education, and talent development. Through ongoing contributions to NoC IP and SoC integration technologies, the Krakow team plays a key role in advancing complex chip design and a broader focus on strengthening Europe’s semiconductor capabilities.
Design & Reuse: Topology and Data Movement in Multi-Die Design
This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well as the need for configurable interconnects to ensure predictable system behavior. The piece also emphasizes the growing importance of unified integration tools to maintain consistency across complex, multi-die architectures.
The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
Modern system-on-chip (SoC) performance is no longer compute-bound. It is increasingly data-movement–bound and wire-limited.
Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs
Arteris and XuanTie have formed a deep partnership, leveraging the Ncore cache-coherent NoC IP as the core to build a “data highway” for high-performance RISC-V SoCs. Ncore paired with the XuanTie C930 delivers 30 GB/s/GHz bandwidth and 110-cycle latency, supporting expansion up to 16 cores. With its scalability, configurability, and safety advantages, Ncore has been validated within the XuanTie ecosystem, helping accelerate RISC-V toward high-performance applications.
Building Secure Chips: Why Hardware Security Assurance Is Now Essential
Hardware security is no longer optional. At DAC 2025, industry leaders share how teams are shifting from traditional verification to measurable security assurance without breaking budgets or schedules. Learn what’s changing, why it matters, and how to build trust into modern SoC design from the start.
Semiconductor Engineering: Importance Of Hardware Security Verification In Pre-Silicon Design
Security in modern semiconductor design must be built in from the start, not validated after the fact. This article explains how pre-silicon hardware security verification relies on two key pillars — functional verification to ensure security features behave correctly, and protection verification to ensure those features cannot be bypassed under real-world conditions. By combining both with measurable security coverage, engineers can identify hidden vulnerabilities, validate system-wide protections, and gain confidence in silicon before tapeout. Learn more in the article.