EDN: Chiplet innovation isn’t waiting for perfect standards
As monolithic SoCs reach their limits, chiplets offer a more scalable and cost-effective path forward. Despite incomplete standards, companies are moving ahead using modular design and flexible interconnects, with Arteris highlighting the role of NoC IP and automation in enabling practical multi-die systems today. Learn more in the article.
EDN: Last-level cache has become a critical SoC design element
As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully configured around real workload behavior, with early decisions on sizing, banking, and partitioning validated through system-level simulation. The article also highlights Arteris’ CodaCache IP as a configurable LLC solution for scalable, intelligent data management across diverse applications. Learn more.
SemiWiki: Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
As RISC-V adoption grows across commercial and government programs, integrating third-party IP cores introduces supply chain security challenges that require structured, design-level assurance. This article highlights a scalable, CWE-based methodology demonstrated by Cycuity (an Arteris brand) with SiFive and BAE Systems that replaces checklist reviews with measurable, reusable security validation artifacts. By templating requirements, properties, and tests, teams can reduce NRE while strengthening confidence across RISC-V implementations. Learn more in the article.
Semiconductor Engineering: AI Energy Gap and Chiplets: Why Data Movement Matters
At the panel discussion at Chiplet Summit 2026, where Arteris was among the experts, participants emphasized that efficient AI chiplets require more than fast physical links like UCIe—they demand smart, system-level architecture around data movement, coherency, and protocol choice. As AI compute outpaces energy efficiency gains, moving data between dies is becoming a major power challenge, making interconnect design a critical factor in overall system performance and efficiency. Learn more in the article.
Electronic Design: Bridging the Gap to Chiplet Interoperability
This article examines the gap between today’s tightly managed multi-die implementations and the long-term vision of true multi-vendor chiplet interoperability. It explains how companies are deploying homogeneous and heterogeneous architectures, why proprietary flows still limit plug-and-play integration, and how standards like UCIe address only part of the challenge. The piece also highlights the role of scalable interconnects, NoC architectures, and Arteris system IP and automation solutions in building the foundation for a more open chiplet ecosystem. Learn more in the article.
EE Times: The Data Dilemma: Cracking the Code of Data Movement for the Next Wave of Semiconductor Innovation
As semiconductor architectures scale toward chiplets, multi-die SoCs, and AI-driven workloads, data movement—not raw compute—has emerged as the primary limiter of performance, power, and scalability. The article argues that network-on-chip fabrics are becoming the true center of gravity in modern designs, responsible for moving massive volumes of data efficiently across XPUs, memory hierarchies, and specialized logic while staying within strict energy and thermal budgets. Learn more in the article.
Semiconductor Engineering: Solving Real-World AI Bottlenecks
This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and positions FlexGen, FlexNoC, and CodaCache as an integrated system IP approach for keeping data close to compute in complex, real-time designs. Learn more in the article.
EDN: AI workloads demand smarter SoC interconnect design
This EDN article explains how AI workloads are pushing traditional SoC interconnect design beyond practical limits, making intelligent automation essential. Physically aware NoC algorithms optimize topology, power, latency, and timing closure, enabling scalable AI SoCs from data centers to the edge, with Arteris highlighted as a leader in automated interconnect innovation. Learn more in the article.
2026 Predictions: System-Level Design, AI-Native Workflows, and the Rise of Multi-Die Compute Fabrics
Explore 2026 semiconductor predictions as AI accelerates system-level design, multi-die compute fabrics, chiplets, 2.5D/3D integration, and AI-native architecture workflows reshape how advanced systems are built and verified.
Advancing Europe’s Automotive Chiplet Vision: Arteris Joins CHASSIS to Accelerate Software-Defined Mobility
Arteris joins CHASSIS, Europe’s open automotive chiplet initiative with advanced NoC and multi-die interconnect technology that accelerates software-defined mobility.