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Presentation

Building Better IP with RTL Architect NoC IP Physical Exploration

Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with Arteris’ FlexNoC 5 and Ncore NoC development frameworks. FlexNoC 5 facilitates up to 5X faster physical convergence of the back-end physical design time and effort.

Presentation

Efficient Scaling of AI Accelerators Using NoC Tiling

Learn about the benefits of using NoC tiling in AI accelerators, seamless data management with NoC solutions and real-world applications for AI vision.

Network-on-Chip (NoC)

Presentation

Is the Missing Safety Ingredient in Automotive AI Traceability?

Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.

Presentation

The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems

Discover how networks-on-chips (NoCs) are revolutionizing AI/ML across sensors, edge devices, and data centers. This video presentation explores how NoCs enable rapid data movement, seamless component integration, and efficient chip-to-chip communication, paving the way for a new era of AI-powered devices.

Podcast

EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling

In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.

Podcast

EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster

Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs.

Podcast

SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski

SemiWiki’s Dan Nenni welcomes Michal Siwinski, CMO of Arteris, for an in-depth discussion of modern design architectures and the crucial role of Network-on-Chips (NoCs).

Podcast

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.

Presentation

Tiled Approach to System Scaling

Today’s large-scale SoCs such as AI accelerators often deploy regular repeating arrays of processor elements. See how tiling accelerates physical design by enabling re-use of hardened physical blocks in addition to logical elements.

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