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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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NoC-Centric System Performance for the Chiplet-Era with Platform Architect
Video

NoC-Centric System Performance for the Chiplet-Era with Platform Architect

Explore how Arteris NoC IPs and Platform Architect enhance system-level analysis for SoC designs in the chiplet era at the Synopsys Virtual Prototyping Day 2025.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
Smart NoC IP - Revolutionizing SoC Design
Video

Revolutionizing Semiconductor Design with Smart NoC IP

Learn how FlexGen Smart NoC IP can optimize and advance your semiconductor design processes. Designed for automotive, data centers, and industrial electronics applications, it enables faster time-to-market and/or multiple design explorations for the most complex systems.
Podcast

EE Times: Automating NoC Design Masters SoC Complexity

In this podcast, Sally Ward-Foxton and Michal Siwinski discuss how FlexGen, smart NoC IP, is revolutionizing NoC design through automation and why this is crucial for today’s chips. How it addresses the growing demands of AI, and what the future holds for NoC technology.
FlexGen Product Tour image
Video

FlexGen Product Tour

Watch an overview showing how FlexGen smart NoC IP generates a network-on-chip for your SoC in minutes. The RTL is correct-by-design, wire length optimized to meet all the specified performance requirements and floorplan constraints of your design.
Accelerating IP Reuse
Video

Accelerating IP Reuse

Semiconductors now rely on up to 1,000 third-party IPs in complex SoCs, requiring seamless integration. Insaf Meliane of Arteris discusses with Semiconductor Engineering how the latest IP-XACT version simplifies automation, abstraction, and system integration.
SemiEngineering Cache Coherency in Heterogeneous Systems
Video

Cache Coherency in Heterogeneous Systems

Why maintaining flexibility in coherency is essential in heterogeneous designs. A video discussion with Semiconductor Engineering’s Ed Sperling.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Optimizing Data Movement In SoCs And Advanced Packages
Video

Optimizing Data Movement in SoCs and Advanced Packages

Andy Nightingale from Arteris talks about the demand for low-latency on-chip communication in increasingly complex devices, which can include chiplets, multiple networks on chip (NoCs), and the need for managing all of this with less power and using a simpler setup.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
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