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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet
Video

Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplet

Explore how smart NoC generation can help optimize your NoC design processes by reducing iterations and bringing unprecedented quality of results.
Optimizing Data Transport Architectures in RISC–V SoCs for AIML Applications
Video

Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications

This presentation covered the challenges and solutions of data–transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC–V–based SoCs.
Accelerating IP Reuse
Video

Accelerating IP Reuse

Semiconductors now rely on up to 1,000 third-party IPs in complex SoCs, requiring seamless integration. Insaf Meliane of Arteris discusses with Semiconductor Engineering how the latest IP-XACT version simplifies automation, abstraction, and system integration.
SemiEngineering Cache Coherency in Heterogeneous Systems
Video

Cache Coherency in Heterogeneous Systems

Why maintaining flexibility in coherency is essential in heterogeneous designs. A video discussion with Semiconductor Engineering’s Ed Sperling.
SemiEngineering Whiteboard Integration Challenges For RISC-V Designs
Video

Integration Challenges for RISC-V Designs

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
SemiEngineering Whiteboard: Promises and Pitfalls of SoC Restructuring
Video

Promises and Pitfalls of SoC Restructuring

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.
Scaling Performance In AI Systems
Video

Scaling Performance in AI Systems

AI designs face increasing challenges in balancing power, performance, and data throughput. Andy Nightingale from Arteris discusses how network-on-chip technology can help alleviate these bottlenecks and accelerate chip time-to-market.
Configurable Test Infra with Mixed-Language & IP-XACT Integration Flow
White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
Scalability A Looming Problem in Safety Analysis
White Paper

Scalability – A Looming Problem in Safety Analysis

Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.
Security in Artificial Intelligence (1)
White Paper

Security in Artificial Intelligence

Unlock insights into AI security challenges & protection strategies. Dive deep into the dual role of AI in cybersecurity.
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