Contact Us
Generic selectors
Exact matches only
Search in title
Search in content
Post Type Selectors

White Papers

White Papers

background-element-24

Sort & Filter

Topics
AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
Year filter
Show More
Latest
Oldest
A-Z
Z-A
Filter by Product
Filter by Solution
16 Results
Sort & Filter
White Paper

Build Secure SoCs from the Start

This eBook examines the hardware security assurance in modern semiconductor design. Discover how to detect vulnerabilities early in the development lifecycle, reduce costly silicon respins, and deliver secure silicon products with greater confidence.
Enabling Comprehensive CWE-based Assurance for RISC-V Processors
White Paper

Enabling Comprehensive CWE-based Assurance for RISC-V Processor 

This paper presents a scalable, Common Weakness Enumeration (CWE)–based security assurance methodology for third-party RISC-V processor IP, developed collaboratively by Cycuity, BAE Systems, and SiFive. The approach adapts the MITRE Corporation CWE framework to systematically derive security requirements, verification properties, and evidence for RISC-V cores treated as third-party IP. By introducing reusable assurance templates, portable security tests, and a “golden model” reference, the methodology reduces non-recurring engineering effort while enabling consistent, repeatable verification across implementations. Demonstrated on all 60 CWEs in scope for SiFive’s X280 processor, results show improved scalability, portability, and efficiency in achieving comprehensive hardware security assurance for the broader RISC-V ecosystem.
Assuring Comprehensive Security Coverage in Hardware Design
White Paper

Assuring Comprehensive Security Coverage in Hardware Design

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience.
Making SoC Integration Simple – Achieve Higher Productivity and Quality
White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.
Configurable Test Infra with Mixed-Language & IP-XACT Integration Flow
White Paper

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
A Design Flow for Critical Embedded Systems
White Paper

A Design Flow for Critical Embedded Systems

In this paper by Airbus, Thales, STMicroelectronics, Arteris and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.
A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
White Paper

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.
AMS System Verification with UVM in SystemC & SystemC-AMS for Autos
White Paper

AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.
Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging
White Paper

Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging

This paper written by Nokia and Mentor Siemens describes an efficient integration flow using Portable Stimulus and IP-XACT flow automation.
CodaCache Helping to Break the Memory Wall
White Paper

CodaCache®: Helping to Break the Memory Wall

This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
Previous
Next Page

No results found

Make sure all words are spelled correctly. Try different, more general, or fewer keywords.

Call to Action